Current manufacturable gate stack Complementary Metal Oxide Silicon (CMOS) FET technology has achieved a minimum effective gate length of 0.35 .mu.m atop a 9 nm thick gate oxide. Denser packing requirements demanded by future generations of CMOS FET technology will require 0.1 .mu.m gate lengths on 2-3 nm thick oxides. Attempts to extend present CMOS FET technology to achieve these objectives have been unsatisfactory.
Currently in CMOS logic, both n-type and p-type transistors have polycrystalline silicon gates which are normally fabricated simultaneously by one reactive ion etching (RIE) step in a RIE plasma tool with controlled gas chemistry. In current plasma etching tools, the n-type polycrystalline Si gate structure tends to etch faster than the p-type gate structure in HBr/Cl2 plasmas commonly used for CMOS FET fabrication. Thus, n-type FET's have a shorter channel length than P-type FET's which is undesired.
One example of an RIE tool for etching polysilicon gates of FET's is described in European Patent document EP 0495524 A1 by K. S. Collins published Jul. 22, 1992. A triode etching system is used to deposit and/or etch numerous materials and uses a dynamic magnetic field to enhance the plasma density.
In U.S. Pat. No. 5,256,245 by D. J. Keller et al. which issued on Oct. 26, 1993, a chamber cleaning method is described enabling the use of a single etch chamber to etch both the dielectric hard mask and the underlying polysilicon film. A gas mix is used to remove oxide residue from the chamber walls that could cause black silicon. The oxygen scavenging gasses are C2F6, CF4, CHF3, and BCl3 are used in the plasma to liberate oxygen produced during the dielectric etch to produce an inert volatile gas which can be pumped from the chamber.
In U.S. Pat. No. 5,242,536 by P. Schoenborn which issued on Sep. 7, 1993, an anisotropic etch process is described for doped and undoped polysilicon films used in gate technology, with gate oxide thicknesses of 20 nm and minimum polysilicon gate lengths of 0.7 .mu.m. The preferred process settings were 80 sccm Cl.sub.2, 55 sccm HBr, 40 sccm He, 270 mTorr pressure, and 0.62 W/cm2 power density. Photo resist is used as the etch mask material over the polysilicon. The process relies on HBr to form the sidewall passivation layer on the polysilicon. It is stated that the process avoids the creation of negative sidewall slopes, notches, and feet in the polysilicon gates.